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- STAGE - Optimisation par simulation TCAD d'un pixel de type HDR GS-F/H
- Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France
- Hardware Verification Senior/Staff/Senior Staff Engineer at Qualcomm Interconnect Technology Center (QITC)
- NoC Verification Engineer - Qualcomm - Guyancourt, France
- ASIC / NoC Power and Solutions Senior/Staff Engineer - Qualcomm - Guyancourt, France
- ASIC / NoC Verification & Solutions Engineer- Qualcomm - Guyancourt, France
- Hardware Verification, Engineer at Qualcomm Interconnect Technology Center (QITC) - France
- Senior Systems Design Engineer - Qualcomm - Sophia or Guyancourt - France
- Senior Systems Verification Engineer - Qualcomm - Sophia or Guyancourt, France
- Principal Data Center AI SoC & System Architect - Qualcomm - Grenoble, France
- Data Center AI SoC & System Architect - Qualcomm - Grenoble, France
- Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France
- Senior Hardware Engineer - SoC Architecture & Design - Qualcomm - Grenoble, France
- Senior HW IP designer - Qualcomm - Guyancourt or Sopia France
- HW IP designer - Qualcomm - Guyancourt or Sophia, France
- Ingénieur Développement de Produit Confirmé
- Ingénieur/Ingénieur.e Process Traitement Thermique ( TTH)
- ALD Engineer
- Layout Scale-Up Engineer
- 3D Chiplet Engineer
- Senior Program Manager (Product Development)
- Hardware Architect and Team Lead
- RTL Verification Engineer
- Front End RTL Designer / SoC integration
- CIFRE - La découpe laser : un process clé pour la singulation des puces en SiC (F/H)
- VIE - Italie - Ingénieur Fiabilité H/F
- CIFRE - Cosmic rays robustness - H/F
- CDI - Flip-Chip Process Development Engineer - Advanced Packaging & Photonics F/H
- CIFRE - Panel Level Package (PLP) development : interfaces characterization - H/F
- CDI - Ingénieur développement de procédés - CMP / Plating
- CDI - Ingénieur(e) Process Gravure Plasma H/F
- CDI - Imager SoC & Digital architect - F/H
- CDI F/H technicien process en Zone Back lap de STMicroelectronics Rousset
- CDI - Ingénieur Vérification Analogique / Mixed-Signal (AMS) - F/H
- CIFRE - Multiscale Electro-Thermal Modeling of Silicon Power Devices
- CDI - Ingénieur vérification numérique - Grenoble - F/H
- CDI - Senior SoC Digital Design Engineer – Digital Mixed-Signal IC F/H
- CDI - Senior SoC Digital Design Engineer – Digital Image Sensor F/H
- CDI - Ingénieur vérification numérique - Paris - F/H
- AGRATE VIE - MDRF Q&R Failure Analysis Engineer F/H
- STAGE – Etude de la capabilité des procédés de packaging avancé – F/H
- CDD - Ingénieur développement de procédés (Lithographie) F/H
- CDD - Ingénieur Développement de Procédés (Chemical and Mechanical Polishing) F/H
- CDD - Ingénieur Développement de Procédés Métal F/H
- Ingénieur produit senior & expert en IA (F/H)
- Ingénieur produit senior & expert en IA (F/H)
- Stage - Computational Geometry f/m - Strategic Student Program
- Staff Layout Design Engineer
- Principal PCIe CXL RTL Design Engineer
- Single Photon Source Lithography Engineer
- Process Engineer - Semiconductor Processes
- ESD Design Expert
- Stage ingénieur : mmW IC Designer Conception d'un amplificateur de puissance RF pour radar automobile évolutif (F/H)
- Stage Ingénieur : L'IA appliquée à l'implémentation physique des circuits numériques (F/H)
- Stage ingénieur : Conception circuits analogiques: Etude du buffer pour une référence de tension ultra précise et invariable dans le temps (F/M)
- Senior SOC Design For Test Engineer
- Stage ingénieur : Génération et qualification de modèles comportementaux pilotées par l’IA (F/H)
- Senior HW Digital Design Verification Engineer
- EMC Design Engineer
- Principal Hardware & IC Functional Safety Architect
- Principal Analog Design Engineer – BMS Production Support
- AMS Verification Engineer
- AMS Verification Engineer
- STAGE - Ingénieur conception Circuit intégré Hyperfréquence - F/H
- STAGE - Evaluation des technologies IA pour la vérification ASIC/FPGA